Researchers Run Surface Code Below Threshold on IBM Heron

The surface code typically requires a perfectly square grid of qubits, each connected to its four nearest neighbors. However, IBM’s Heron processors use a heavy-hex layout, which is sparser and more spread out, in a configuration that doesn’t naturally suit the surface code. Despite this mismatch, researchers at USC and Quantum Elements successfully ran the surface code on Heron processors.

Their paper, “Surface code scaling on heavy-hex superconducting quantum processors,” was peer-reviewed and published in Nature Communications. Daniel Lidar, director of the USC Center for Quantum Information Science & Technology and chief scientific officer at Quantum Elements, co-authored the paper with quantum research scientist Arian Vezvaee and others. The experiments were conducted on two actual IBM Heron-generation chips, confirming that this was not a simulation.

The Surface Code’s Ideal Layout vs. Heron’s Reality

Quantum error correction distributes the information of one reliable logical qubit across multiple unstable physical qubits. The surface code is a popular method for this, which arranges physical qubits in a square lattice and constantly checking their neighbors to detect errors before they accumulate. This geometry is crucial; the code assumes each qubit can communicate with its four surrounding qubits, an assumption fundamental to its error-detection mechanism.

Heron’s heavy-hex design, however, connects qubits more loosely, a reasonable engineering choice for other applications. Mapping a square code onto this hardware necessitates routing information over longer paths.

This rerouting creates a problem:

Routing takes time. As the chip reconfigures qubits to simulate the required connectivity, some qubits remain idle. Idle qubits are not dormant; they drift, accumulate noise, and develop errors during this waiting period. As the code grows, so does the waiting time and the noise accumulation. Thus, the very mechanism designed for protection can be undermined by the delays involved in its setup.

Orbit: The Solution

The team combined two strategies. First, they used a depth-efficient version of the surface code, which minimizes the idle time of qubits. Second, and more notably, they employed dynamical decoupling.

Dynamical decoupling is a technique used to quiet a waiting qubit. It involves applying a precisely timed sequence of pulses that effectively cancel out the slow noise attempting to corrupt it. This can be likened to noise-canceling headphones for a qubit. Lidar helped develop the theory and practice of this method years ago, which later became the foundation for Quantum Elements’ Qiskit Function, Orbit. Therefore, this decoupling is not a mere lab hack but a productized technique integrated into their error-correction run.

Together, these two approaches sufficiently suppressed idle-time noise, allowing the code to function as intended.

Below Threshold, and Directional

The significant outcome for the team is the achievement of below-threshold performance. A code operating below threshold improves its logical qubit’s performance as it scales up. Conversely, above threshold, adding more physical qubits merely introduces more points of failure, making error mitigation increasingly difficult. Below-threshold performance is essential for scalable error correction.

The USC and Quantum Elements team observed subthreshold scaling, but with a catch: it was directional. Growing the code along one axis increased its protection against a specific type of logical error. This directional improvement represents a genuine scaling signal on hardware not originally designed for this code. The paper acknowledges that this protection is narrower than comprehensive, all-directional protection.

Lidar emphasized the critical role of decoupling:

“We found that only by leveraging the dynamical decoupling techniques deployed in Quantum Elements’ Qiskit Function, Orbit, we were able to demonstrate the expected improvements as the surface code’s distance parameters increased.” 

Without these pulses, idle noise would overwhelm the system; with them, scaling becomes evident.

What This Is and Is Not

There is no claim of quantum advantage here. The paper does not suggest that this work outperforms a classical computer for any useful task, nor does it pretend to. This is also not a fault-tolerant quantum computer. Fault tolerance, or the ability to suppress errors sufficiently for long, reliable computations, is the ultimate goal, and the team presents their result as a step toward it, not an arrival. What they demonstrated is the directional subthreshold scaling of logical qubits on hardware whose geometry is inherently challenging for the surface code.

The “first step” language comes directly from the team. Quantum Elements CEO Izhar Medalsy stated it was “just the first step toward implementing entangled logical qubits,” which the company plans to detail later. Entangled logical qubits were not presented in this paper, so future claims should be viewed as roadmap items.

The established result is significant. A processor does not need to be custom-built for the surface code’s square geometry to benefit from its scaling advantages. This relaxes a constraint that hardware designers have faced. Chips must meet numerous engineering demands simultaneously, and if scalable error correction strictly mandated a specific layout, many otherwise excellent designs would be hindered. 

This research suggests the surface code can be adapted to other superconducting architectures, provided appropriate decoupling techniques are used to mitigate idle qubit noise.

In summary, a square code was successfully run on hexagon hardware, exhibiting growth and improvement in one direction, thanks to meticulous pulsing that suppressed noise. This represents a real measurement on real chips. However, it remains far from a machine capable of tasks beyond the scope of a conventional laptop, and no one involved suggests otherwise.