Iceberg Quantum, Diraq Map qLDPC Codes to Spin Qubits

Let’s say there was a quantum error-correction scheme that promised to protect data using significantly fewer physical qubits than standard methods. Now, think of that scheme as receiving a major announcement before anyone has built the fault-tolerant machine it’s intended for. This describes the September 2026 news from Iceberg Quantum and Diraq.

The two companies announced they have mapped Iceberg’s Pinnacle qLDPC architecture onto Diraq’s silicon spin-qubit platform using NVIDIA’s CUDA-Q Logical software layer. Though this might sound like a hardware demonstration, closer inspection reveals it to be a design and simulation study.

What Was Announced

First, let’s clarify the nature of this announcement, as everything else hinges on it. The information came via a press release distributed by trade publications. The foundational work for Pinnacle is a cited arXiv paper. The spin-qubit “result” itself is a mapping exercise combined with noise simulations. No fabricated array has run a code cycle here.

The companies’ own descriptions state they’ve embedded Pinnacle “within Diraq’s hardware architecture” and conducted “shuttling-aware noise simulations.” This amounts to software modeling of how the architecture would perform on the hardware.

Diraq’s CEO, Andrew Dzurak, claims this involves placing “the most advanced fault-tolerant error-correction technology on top of our hardware,” which suggests a projected logical performance increase “by an order of magnitude.” These assertions originate solely from Diraq and Iceberg; no independent laboratory has measured these qubits.

The qLDPC Idea, In One Analogy

Error correction addresses a fundamental problem: quantum bits lose their state. A single physical qubit holds a fragile state that quickly decays. To protect a reliable logical qubit, its information is spread across many physical qubits, and these are constantly checked for errors.

These checks are parity checks. They measure whether groups of qubits agree with each other. Disagreement indicates an error has occurred, but it doesn’t reveal the specific data. The traditional approach, the surface code, requires a large number of physical qubits per logical qubit. Think of it like assigning a security guard to every square inch of a warehouse.

Quantum low-density parity-check codes (qLDPC) aim to reduce this “guard count.” The “low-density” aspect means each check involves only a few qubits, and each qubit participates in only a few checks—a sparse arrangement. This sparsity is what theoretically allows qLDPC codes to protect the same information with fewer physical qubits. Iceberg’s core proposition, according to its website, is to reduce error-correction overhead “by over an order of magnitude.”

The persistent challenge with qLDPC has been connectivity. Sparse checks often require qubits that are physically distant on the chip to communicate, and most hardware designs struggle with non-local connections.

Why Spin Qubits, And Why Shuttling

Diraq produces spin qubits in silicon using the same CMOS process employed for conventional microchips. This is their advantage: dense, small, and compatible with an existing, scalable semiconductor fabrication pipeline.

Spin qubits manage connectivity by physical movement. Qubits are shuttled across the array to interact with distant ones. However, each movement incurs a cost, as a shuttled qubit accumulates errors along its path. Therefore, the design challenge for Pinnacle on this platform was to integrate non-local checks while minimizing shuttling distances.

The companies state that Pinnacle addresses this through its modular block design. Non-local connectivity is confined within these blocks, never spanning the entire chip. They optimized codes and shuttling schedules to make sure that qubit movement does not add more to the error budget than the physical gates already do. If the simulation holds true, this represents a clever engineering feat. However, it remains a simulation.

The Numbers, And What They Rest On

The headline figure is 1,000 logical qubits from 150,000 physical qubits, a number derived from Diraq’s white paper, “The Case for Silicon.” The companies also report that hardware-aware qubit counts aligned with the Pinnacle paper’s estimates to within 5%. NVIDIA’s CUDA-Q Logical successfully compiled logical primitives, including adder circuits, down to hardware-level operations.

Now for the less impressive details.

• Reported
• Grounding available
• 1,000 logical / 150,000 physical qubits
• From Diraq’s own white paper, not measured
• 5% agreement with Pinnacle paper
• Simulation vs. paper estimate
• Order-of-magnitude logical gain
• Projected, company-stated
• Shuttling noise handled
• Numerical simulation only

There are no measured gate fidelities, no readout fidelities, no syndrome data from a real chip, no logical error rates from a fabricated array, and no decoder benchmarks against a running device. The entire demonstration exists within the realm of design and modeling.

Scope: What This Is (And Isn’t)

This is not a fault-tolerant quantum computer. It is not a logical qubit that has suppressed errors on hardware. No claim of quantum advantage was made, and reproducing a resource estimate in software would not establish one. What the companies have shown is that Pinnacle can be expressed on Diraq’s architecture without demanding more from the platform than a surface code would, and that a compilation toolchain can manage this end-to-end.

This is genuinely useful. Co-designing an error-correction architecture with real hardware constraints in mind, before the hardware even exists, can save years of developing the wrong approach. NVIDIA’s Sam Stanwyck aptly describes it as testing codes against constraints “before the hardware is built.” This tooling aspect is the strongest part of the announcement.

The result would be significantly bolstered by a fabricated spin-qubit array running repeated code cycles, demonstrating logical error rates that decrease with added qubits, and verified by an independent party. Until then, this remains a promising blueprint supported by a robust simulator. Meanwhile, policy discussions continue, with Brussels preparing a Quantum Act for 2026 while hardware developers debate qubit counts that are not yet physically realized.

A design that functions well in a noise model is a good step. It is not yet a machine.